1. Technical Field
The present disclosure relates to a semiconductor circuit and, more particularly, to a memory subsystem capable of using bank identification (ID), a controller and a memory device included in the memory subsystem, and a method of operating the memory subsystem.
2. Discussion of Related Art
FIG. 1 is a block diagram of a conventional memory subsystem 10. The memory subsystem 10 includes a controller 20 and a plurality of memory banks 30-1 through 30-n, where “n” is a natural number. The first memory bank 30-1 includes a plurality of memory devices 31-1 and 32-1 and the n-th memory bank 30-n includes a plurality of memory devices 31-n and 32-n. 
The controller 20 and the memory banks 30-1 through 30-n share a 16-bit data bus 21 including a pair of 8-bit data buses. The controller 20 provides a clock signal CLK, an address signal ADD, bank select signals BS#0 to BS#n, and at least one control signal CTRL for controlling each of the memory devices 31-1, 32-1, 31-n, and 32-n. 
In the conventional memory subsystem 10, when the number of memory banks 30-1 through 30-n increases, the number of bank selection signals BS#0 through BS#n that must be generated by the controller 20 to select the banks 30-1 through 30-n is increased by an increment of the number of the banks 30-1 through 30-n. Accordingly, the number of pins of the controller 20 for outputting the bank selection signals BS#0 through BS#n is also increased and, therefore, the design of the controller 20 becomes complicated. As a result, the design of the memory subsystem 10 including the controller 20 is also complicated. Moreover, when the memory devices 31-1, 32-1, 31-n, and 32-n are implemented by flash memory, for example, flash electrically erasable programmable read-only memory (EEPROM), the internal delay time of the flash EEPROM becomes relatively longer.
Furthermore, each of the memory devices 31-1, 32-1, 31-n, and 32-n does not include a port or a pin for outputting a signal concerning its own operating status, for example, a write status, a read status, an erase status, or a program status, Accordingly, the controller 20 detects the operating status of each of the memory devices 31-1, 32-1, 31-n, and 32-n by receiving operating status signals from the memory devices 31-1, 32-1, 31-n, and 32-n via the data bus 21 and, therefore, the controller 20 cannot accurately check the operating statuses of the memory devices 31-1, 32-1, 31-n, and 32-n at a desired time. In other words, while the controller 20 is transmitting and receiving data to and from one of the memory banks 30-1 through 30-n via the data bus 21 the data exists on the data bus 21 and, therefore, the controller 20 cannot check the operating status of a desired one of the memory banks 30-1 through 30-n. 